Enabling Non-Volatile Memory Technologies
Contact: Onur Mutlu
Existing main memory systems are built using DRAM (dynamic random access memory) storage technology. While DRAM memories can be constructed with high bandwidth and low latency, it is facing significant challenges. First, the demand for main memory capacity and bandwidth is increasing, with the increasing number of cores placed on a single chip, data-intensive applications demanding more data, and the increasing need/trend for consolidation of many applications on a single system in cloud computing, heterogeneous CPU/GPU, and mobile systems. Yet, DRAM capacity is difficult to scale up as we go into the future. Second, power and energy consumption of DRAM-based main memory is becoming a significant concern: DRAM memory consumes power even when idle and needs periodic refresh of data cells as it is volatile. Third, the scaling of DRAM technology to smaller feature sizes is becoming increasingly difficult due to challenges in scaling down the storage element, the capacitor. Scaling of DRAM cells has provided many benefits, including increased storage capacity per unit area, reduced cost, and higher density, which are becoming challenging to obtain. As a result, DRAM alone will likely be inefficient and insufficient in building the main memory hierarchy of future systems. Our goal in this research is to rethink the main memory hierarchy in the presence of the challenges described above and explore the potential of new memory technologies to replace or augment DRAM.
Non-volatile memory/storage (NVM) technologies such as Flash, Phase Change Memory (PCM), and magnetic memory (MRAM) are promising due to their anticipated capacity benefits, non-volatility, and zero idle energy. This project examines the use of NVM technologies as part of main memory, accessed directly using load/store instructions in order to overcome the challenges associated with building a DRAM-only main memory. Unfortunately, these emerging memory technologies have serious shortcomings compared to DRAM, which need to be overcome: 1) they are significantly slower to access, 2) they have very low endurance, 3) they have very high write latency and write energy. Our goal is to redesign the memory hierarchy to overcome these challenges and exploit the new opportunities of NVM technologies. We are rethinking the entire virtual memory design and main memory system to integrate especially Flash and PCM as fundamental main memory components, with the goal of designing a significantly more energy-efficient, cheaper, scalable, high-capacity, and more capable memory/storage system using a hybrid of DRAM, PCM, and Flash memories.
- Asymmetry-aware Execution Placement on Manycore Chips. Alexey Tumanov, Joshua Wise, Onur Mutlu, Gregory R. Ganger. In Proc. of the 3rd Workshop on Systems for Future Multicore Architectures (SFMA'13), EuroSys'13, Apr. 14-17, 2013, Prague, Czech Republic.
Abstract / PDF [703K]
- Application-to-Core Mapping Policies to Reduce Memory System Interference in Multi-Core Systems. Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi. Proceedings of the 19th International Symposium on High-Performance Computer Architecture (HPCA 2013), Shenzhen, China, February 2013.
Abstract / PDF [623K]
- MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems. Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, Onur Mutlu. Proceedings of the 19th International Symposium on High-Performance Computer Architecture (HPCA 2013), Shenzhen, China, February 2013.
Abstract / PDF [607K]
- Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture.
Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu. Proceedings of the 19th International Symposium on High-Performance Computer Architecture (HPCA), Shenzhen China, February 2013.
Abstract / PDF [3.17M]
- Row Buffer Locality Aware Caching Policies for Hybrid Memories. HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael A. Harding, Onur Mutlu. Proceedings of the 30th IEEE International Conference on Computer Design (ICCD 2012), Montreal, Quebec, Canada, September 2012.
Best paper award in Computer Systems and Applications track.
Abstract / PDF [577K]
- A Case for Small Row Buffers in Non-Volatile Main Memories. Justin Meza, Jing Li, Onur Mutlu. Proceedings of the 30th IEEE International Conference on Computer Design (ICCD 2012), Poster Session, Montreal, Quebec, Canada, September 2012.
Abstract / PDF [172K]
- A Case for Exploiting Subarray-level Parallelism (SALP) in DRAM. Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu. Proceedings of the 39th International Symposium on Computer Architecture, June 2012.
Abstract / PDF [927K]
- RAIDR: Retention-Aware Intelligent DRAM Refresh. Jamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu. In Proceedings of the 39th International Symposium on Computer Architecture, Portland, Oregon, June 9-13th, 2012.
Abstract / PDF [480K]
- Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems.
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lavanya Subramanian, Gabriel H. Loh, Onur Mutlu. The 39th International Symposium on Computer Architecture (ISCA), Portland, Oregon, June 9-13th, 2012.
Abstract / PDF [700K]
- Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management. Justin Meza, Jichuan Chang, HanBin Yoon, Onur Mutlu, Parthasarathy Ranganathan. IEEE Computer Architecture Letters (CAL), May 2012.
Abstract / PDF [184K]
- Persistent, Protected and Cached: Building Blocks for Main Memory Data Stores. Iulian Moraru, David G. Andersen, Michael Kaminsky, Nathan Binkert, Niraj Tolia, Reinhard Munz,Parthasarathy Ranganathan. Carnegie Mellon University Parallel Data Lab Technical Report CMU-PDL-11-114v2, Nov. 2012. Supersedes CMU-PDL-11-114. Dec. 2011.
Abstract / PDF [1.0M]
- Row Buffer Locality-Aware Data Placement in Hybrid Memories. HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael Harding, Onur Mutlu. SAFARI Technical Report, TR-SAFARI-2011-005, Carnegie Mellon University, September 2011.
Abstract / PDF [272K]
- Memory Power Management via Dynamic Voltage/Frequency Scaling. Howard David, Chris Fallin, Eugene Gorbatov, Ulf R. Hanebutte, Onur Mutlu. Proceedings of the 8th International Conference on Autonomic Computing (ICAC), Karlsruhe, Germany, June 2011.
Abstract / PDF [463K]
- Phase Change Memory Architecture and the Quest for Scalability. Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger. Communications of the ACM (CACM), Research Highlight, Vol. 53, No. 7, pages 99-106, July 2010.
Abstract / PDF [1.34M]
- Phase Change Technology and the Future of Main Memory. Benjamin C. Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, Doug Burger. IEEE Micro, Special Issue: Micro's Top Picks from 2009 Computer Architecture Conferences (MICRO TOP PICKS), Vol. 30, No. 1, pages 60-70, January/February 2010.
Abstract / PDF [600K]
- Architecting Phase Change Memory as a Scalable DRAM Alternative. Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger. Proceedings of the 36th International Symposium on Computer Architecture (ISCA), pages 2-13, Austin, TX, June 2009.
Abstract / PDF [2.6M]
We thank the members and companies of the PDL Consortium: Actifio, American Power Conversion, EMC Corporation, Emulex, Facebook, Fusion-io,Google, Hewlett-Packard Labs, Hitachi, Huawei Technologies Co., Intel Corporation, NEC Laboratories, NetApp, Inc., Oracle Corporation, Panasas, Samsung Information Systems America, Seagate Technology, STEC, Inc., Symantec Corporation, VMware, Inc., and Western Digital for their interest, insights, feedback, and support.